1. Field of the Invention
The present invention relates generally to a methodology for designing a digital logic circuit. It particularly relates to a method and apparatus for providing dynamic logic circuit synthesis techniques that generate an optimal digital circuit that minimizes critical-path delay, residue logic, and circuit area.
2. Background
Dynamic logic circuit families (e.g., domino logic) have long been employed in high performance microprocessors and other commercially important semiconductor products as a solution for logic blocks needing more speed and functionality than found with standard CMOS circuits. xe2x80x9cDomino logicxe2x80x9d refers to a circuit arrangement in which there are several series coupled logic stages having precharged output nodes (the stages may be referred to as a xe2x80x9cdomino blockxe2x80x9d). The output node of each logic stage is precharged to a first logic level during a xe2x80x9cprecharge phasexe2x80x9d. During an xe2x80x9cevaluation phasexe2x80x9d, one or more signals may be applied to the first stage of the domino block. Depending upon the input signals, the output node may transition to a second logic level it xe2x80x9cevaluatesxe2x80x9d. As each domino stage in the chain evaluates, the output of the next domino stage may be enabled to switch. Since the precharged nodes xe2x80x9cfallxe2x80x9d in sequence, the operation has been analogized to falling dominoes, and hence the name for this type of circuit arrangement.
An advantage of dynamic logic is the capability to supply much more dense functionality in a given time period while providing higher drive capability than is possible with standard static CMOS logic. Dynamic logic gates are precharged and selectively discharged through a n-device logic tree at every stage or every other stage. They do not require a p-logic tree as in standard push-pull static CMOS and, therefore, the capacitive loads on both the inputs and the outputs can be much smaller. Additionally, transition times and switching speeds can be faster by avoiding use of series-connected p-gates in the critical switching path on the n-logic stages and due to smaller contention currents. Therefore, the logic function can be much wider (accepting any number of inputsxe2x80x94e.g. four or more). Especially in highly scaled technologies, NOR and NAND-NOR logic with greater than ( greater than ) 4 inputs to a gate is not viable in static gates. It can have high speed and reasonable drive capability in dynamic gates. The major disadvantages of dynamic logic are the larger design complexity and expertise that are required for effective operation as well as the higher power and larger, higher cost circuit area that is needed, especially if the dynamic circuitry is not well deployed and well designed.
Custom, expert, manual design has been necessary to use dynamic circuits effectively and safely as solutions to critical, complex logic on microprocessors. Although dynamic logic design can have an important impact on chip (processor) performance, it may cost a disproportionate share of effort and risk, even though used on a small percentage of the processor. An automated or semi-automated synthesis system for domino logic would greatly improve design productivity and chip convergence.
Logic synthesis is a key factor in using dynamic logic to its best advantage and for minimizing its costs and risks. Typically, logic synthesis process can be divided into a technology independent optimization phase and a technology mapping phase. The technology independent optimization phase performs logic minimization and structuring in order to find a good multilevel structure for mapping to an ECAD (electronic computer-aided design) domino library.
Technology mapping is the process of implementing a Boolean network using gates from a technology library. The goal is to produce a circuit with minimal critical-path delay and area via optimal use of gates in the library. Traditional technology mapping techniques developed both by EDA vendors and universities have been primarily targeted at standard static CMOS circuits and are not well-suited for domino logic. They are generally targeted at logic blocks with less critical requirements than those needing dynamic circuitry and at users with less high speed circuit design experience than the dynamic logic designer. These mapping techniques have several disadvantages for application to high-speed dynamic circuitry including: 1) the use of pattern generation and graph representation of logic functions, that result in pattern explosion (exponential growth in complexity for wide gates), 2) lack of support for dynamic design styles and configurations, 3) lack of support for monotonic logic networks (required for dynamic logic structures do to its precharge) or control over inversion placement, and 4) initially de-compose networks using only simple gates such as 2-input NAND (or 2-input NOR). Therefore, there is a need to provide a technology mapping solution that effectively synthesizes an optimal digital logic (e.g., domino logic) circuit having wider gate inputs and improvements in circuit delay.